1. Field of the Invention
The present invention relates to a semiconductor memory device such as an SRAM (static random access memory) and a method of manufacturing the same, inclusive of forming a wiring arrangement therein.
2. Description of the Prior Art
It is generally known that SRAMs are classified into high-resistance load type, TFT load type and full CMOS type, of which the former two types are advantageous in the point that the memory cell size is reducible, and therefore these types are considered dominant in the recent 4-Mbit and 16-Mbit SRAMs.
In comparison therewith, the cell size in the full CMOS type SRAM tends to be greater since six MOS transistors are required per cell.
In any SRAM of the high-resistance load type and TFT load type, it is difficult to enhance the operating stability of each cell and the soft error tolerance. Meanwhile the full CMOS type SRAM has an advantage that the operating stability of each cell and the soft error tolerance can be enhanced. It is therefore urgently requisite to raise the integrating density of the full CMOS type SRAM as high as possible. In order to meet such requirements, it is apparently preferred that an SRAM be composed of an SOI type semiconductor device, since in an SOI layer, a p-channel MOS transistor and an n-channel MOS transistor can be formed relatively in the proximity of each other. However, due to the fact that reduction of both the width of each MOS transistor and the interval between adjacent MOS transistors is restricted by the resolution of photolithography, it has been eventually impossible heretofore to attain high-density integration differently from the high-resistance load type or TFT load type SRAM.
In the SRAM, it is necessary to supply a power to each of memory cells. When data is written in a memory cell, a current flows from a power line to a bit line via a load means (a high resistance load or a load MOS transistor) and a switching (word) MOS transistor. The current reaches its maximum at the data writing time, and consequently a voltage drop is caused in the power line. Such voltage drop is equivalent to the product of the maximum current and the parasitic resistance of the power line. And it is necessary to minimize the value of such voltage drop.
In a SRAM where the load is a high-resistance element of polycrystal silicon, the current flowing from the power line to the bit line at the data writing time can be sufficiently reduced since the load has a high resistance value, so that the power line may be composed of polycrystal silicon whose sheet resistivity is relatively high. And practically, polycrystal silicon is used to compose the power line.
Meanwhile, in a full CMOS type SRAM where an n-channel MOS transistor is employed as a driver transistor and a p-channel MOS transistor as a load transistor respectively, the current I flowing at the writing time becomes considerably great as the load consists of a p-channel MOS transistor. Therefore a great voltage drop occurs in the power line unless the resistance R of the power line is reduced to an extremely small value. Although such full CMOS type SRAM has a problem of a great voltage drop in the power line, there also exists a remarkable advantage with regard to superior operating stability of each cell and a high soft error tolerance.
In an exemplary case of a 4-Mbit full CMOS type SRAM where the current I flowing in one cell at a data writing time is approximately 60 .mu.A, the maximum voltage drop caused in a power line is expressed as EQU .DELTA.V=8RI
Multiplying the value RI by 8 is based on the reason that the data is written in 8-bit cells simultaneously.
The maximum permissible value of the voltage drop .DELTA.V caused in the power line is not so great if there are taken into consideration the supply voltage variations and the conditions (determined principally by the current driving capabilities of both transistors in the inverter) where an inverter (constituting a flip-flop) in the memory cell performs its proper function. Supposing now that the maximum permissible voltage drop is 1 V, the resistance R of the power line to satisfy this condition is expressed as follows with the margin ignored. EQU R.ltoreq.1/8.multidot.I.apprxeq.2000 [.OMEGA.]
It signifies that the resistance R of the power line needs to be less than 2 k.OMEGA.. However, considering the necessity to ensure the margin, it is practically requisite that the resistance R should be smaller than 1 k.OMEGA..
In the full CMOS type SRAM, therefore, it is customary that the power line 1 for supplying a power directly to cells a.sub.1, a.sub.2. . . . a.sub.n as shown in FIG. 1 is composed of aluminum likewise the aforementioned power line 2.
However, if the power line 1 for supplying a power directly to the cells a.sub.1, a.sub.2. . . . a.sub.n is also composed of aluminum similarly to the power line 2 as described above, it follows that the area occupied by the cell array becomes wide to consequently raise a problem of difficulty in attaining a high integration density of the RAM.
Such technical difficulty is derived from the fact that some other elements to be composed of a first aluminum film 1Al are also existent in the RAM. It is generally customary that bit lines are composed of a second aluminum film 2Al, whereas a ground line and a main word line need to be composed of the first aluminum film 1Al. In case even the power line 1 in FIG. 1 is also composed of the film 1Al, the desired high integration density of the RAM is hardly realizable due to the necessity of ensuring the required line and space (L & S) of the film 1Al.
In an exemplary case where a main word line is composed of an aluminum film 1Al, it is ordinary that a word line is composed of polycrystal silicon. However, in an SRAM based on a divided word line system, a main word line is composed of an aluminum film 1Al while a section word line is composed of polycrystal silicon. And in any 1-Mbit or 4-Mbit SRAM, the divided word line system is adopted.
Thus, in the constitution where the power line for supplying a required voltage directly to each memory cell is composed of an aluminum film 1Al, it is difficult to attain a further higher integration density.